The present invention relates to transferring data via communication protocols, and more particularly to transferring data through a buffer.
Many different communication protocols exist to control data communication. Such protocols include 10 Gigabit Medium Independent Interface (XGMII) and System Packet Interface Level 4 Phase 2 (SPI-4 Phase 2 or “SPI-4”, as used herein). As an example, SPI-4 is a versatile general-purpose interface for exchanging packets anywhere within or among communication systems, as it is an interface for packet and cell transfer between a physical layer (PHY) device and a link layer device. The SPI-4 protocol expresses packets in words of fixed length, with new packets byte-aligned to the start of a word. For some packet lengths, the end of a packet must be padded with idles to fill the last word. When data is passed between systems with different protocols, this padding has to be changed to suit the new word length.
In higher speed applications, there are no extra cycles to handle padding operations. Thus there is a need to ‘keep up’ with input data by handling any padding requirements in a single cycle. In very high speed interfaces, internal logic may have to operate on several consecutive words, meaning that a single cycle may have to deal with data from more than one packet, while also having to deal with padding requirements between packets. Thus a need exists to appropriately buffer and format variable length data packets.